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quad, 16 bit dac with 10ppm/c max on- chip reference in 14-lead tssop preliminary technical data ad5666 features low power quad 16 bit dac 12-bit accuracy guaranteed 14-lead tssop package on-chip 1.25/2.5v, 10ppm/c reference power-down to 200 na @ 5v, 50 na @ 3v 3v/5v power supply guaranteed monotonic by design power-on-reset to zero or midscale three power-down functions hardware /ldac and /clr functions sdo daisy-chaining option rail-to-rail operation temperature range -40c to +125c applications processcontrol data acquisition systems portable battery powered instruments digital gain and offset adjustment programmable voltage and current sources programmable attenuators power- on reset ldac clr interface logic din sync sclk i nput register i nput register i nput register i nput register d ac register dac register dac register dac register string dac c string dac a string dac b string dac d buffer buffer buffer buffer ldac power-down logic v out b v out c v out d v dd v out a v ref
sdo por gnd figure 1. functional block diagram general description the ad5666 dac is a low power, quad, 16-bit buffered voltage-out dac. the part operates from a single +2.7v to +5.5v, and is guaranteed monotonic by design. the ad5666 has an on-chip referenc e with an internal gain of two. the ad5666-1 has a 1.25 v 10ppm/c max reference and the ad5666-2 has a 2.5v 10ppm/c max reference. the on- board reference is off at power-up allowing the use of an external reference. the internal reference is turned on by writing to the dac. the part incorporates a power-on-reset circuit that ensures that the dac output powers up to zero volts (por pin low) or midscale (por pin high) and remains there until a valid write takes place. the part contains a power-down feature that reduces the current consumption of the device to 200na at 5v and provides software selectable output loads while in power-down mode for any or all dacs channels. the outputs of all dacs may be updated simultaneously using the /ldac function, with the added functionality of selecting through software any number of dac channels to synchronize. there is also an asynchronous active low / clr that clears all dacs to a software selectable code - 0 v, midscale or fullscale . the ad5666 utilizes a versatile th ree-wire serial interface that operates at clock rates up to 50 mhz and is compatible with standard spi?, qspi?, microwire? and dsp interface standards. its on-chip precision output amplifier allows rail-to- rail output swing to be achieved. product highlights 1. quad 16-bit dac; 12-bit accuracy guaranteed. 2. on-chip 1.25/2.5v, 10ppm/c max reference. 3. available in 14-lead tssop package. 4. selectable power-on-reset to zero volts or midscale. 5. power-down capability. when powered down, the dac typically consumes 50na at 3v and 200na at 5v. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to chan ge without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the proper ty of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.326.8703 ? 2004 analog devices, inc. all rights reserved.
ad5666 preliminary technical data rev.pra | page 2 of 23 table of contents features .......................................................................................... 1 applications................................................................................... 1 general description..................................................................... 1 product highlights ....................................................................... 1 ad5666?specifications.................................................................... 3 timing characteristics..................................................................... 3 pin configuration and function descriptions........................... 10 absolute maximum ratings.......................................................... 11 esd caution................................................................................ 11 terminology................................................................................ 11 ad5666?typical performance characteristics .......................... 13 general description................................................................... 16 serial interface ............................................................................ 16 microprocessor interfacing............................................................ applications ..................................................................................... outline dimensions ....................................................................... 23 ordering guide ............................................................................... revision history revision 0: initial version
preliminary technical data ad5666 rev. pra| page 3 of 23 ad5666?specifications (v dd = +4.5 v to +5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; external vref = vdd; all specifications t min to t max unless otherwise noted) table 1. a grade b grade parameter min typ max min typ max unit b ersion 1 , 2 conditions/comments static performance 3,4 resolution 16 16 bits relative accuracy 32 16 lsb see figure 4 differential nonlinearity 1 1 lsb guaranteed monotonic by design. see figure 5. load regulation 2 2 lsb/ma ddref5, midscale iout=0ma to 15ma sourcing/sinking zero code error +1 +9 +1 +9 mv all zeroes loaded to dac register. see figure 8. zero code error drift 3 20 20 v/c full-scale error -0.15 -1.25 -0.15 -1.25 % of fsr all ones loaded to dac register. see figure 8. gain error 0.7 0.7 % of fsr gain temperature coefficient 5 5 ppm of fsr/c offset error 1 9 1 9 mv offset temperature coefficient 1.7 1.7 v/c dc power supply rejection ratio 6 ?80 ?80 db v dd 10% dc crosstalk 6 28 28 v r l = 2 k. to gnd or v dd 3.5 3.5 v/ma due to load current change -7.3 -7.3 v due to powering down (per channel) output characteristics 6 output voltage range 0 v dd 0 v dd v capacitive load stability 470 470 pf r l = 1000 1000 pf r l =2 k dc output impedance 1 1 short circuit current 50 50 ma v dd =+5v power-up time 10 10
ad5666 preliminary technical data rev.pra | page 4 of 23 a grade b grade parameter min typ max min typ max unit b version 1 , 2 conditions/comments reference input impedance 14.6 14.6 k ? ? output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 1 v dd ? 1 i source = 2 ma high impedance leakage current 1 1 a high impedance leakage current 5 5 pf power requirements v dd 4.5 5.5 4.5 5.5 v all digital inputs at 0 or v dd dac active and excluding load current i dd (normal mode) 8 0.5 4 0.5 4 ma v ih =v dd and v il =gnd i dd (all power-down modes) 9 0.2 1 0.2 1 a v ih =v dd and v il =gnd power efficiency i out /i dd 89 89 % i load =2 ma, v dd =+5 v
preliminary technical data ad5666 rev. pra| page 5 of 23 ac characteristics 1 (v dd = +4.5 v to +5.5 v; r l = 2 k to gnd; c l = 200 pf to gnd; external vref = vdd; all specifications t min to t max unless otherwise noted) notes 1 guaranteed by design and characterization; not production tested. 2 see the terminology section. 3 temperature range (y version): ?40 c to +125 c; typical at +25 c. specifications subject to change without notice. parameter 2 min typ max unit b version 1 conditions/comments output voltage settling time ad5666 8 10 s ? to ? scale settling to 2lsb settling time for 1lsb step slew rate 1 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry. see figure 21. reference feedthrough 100 db sdo feedthrough 4 nv-s daisy chain mode; sdo load is 10pf digital feedthrough 0.5 nv-s digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz vref = 2v 0.1 v p-p. total harmonic distortion -80 db vref = 2v 0.1 v p-p. frequency = 10khz output noise spectral densi ty 120 nv/hz dac code=8400 h , 1khz 100 nv/hz dac code=8400 h , 10khz output noise 15
ad5666 preliminary technical data rev.pra | page 6 of 23 ad5666?specifications (v dd = +2.7 v to +3.6 v; r l = 2 k to gnd; c l = 200 pf to gnd; external vref = vdd; all specifications t min to t max unless otherwise noted) table error main document only. . a grade b grade parameter min typ max min typ max unit b ersion 1 , 1 conditions/comments static performance 3,4 resolution 16 16 bits relative accuracy 32 16 lsb see figure 4 differential nonlinearity 1 1 lsb guaranteed monotonic by design. see figure 5. load regulation 4 4 lsb/ma ddref3, midscale iout=0ma to 7.5ma sourcing/sinking zero code error +1 +9 +1 +9 mv all zeroes loaded to dac register. see figure 8. zero code error drift 1 20 20 v/c full-scale error -0.15 -1.25 -0.15 -1.25 % of fsr all ones loaded to dac register. see figure 8. gain error 0.7 0.7 % of fsr gain temperature coefficient 5 5 ppm of fsr/c offset error 1 9 1 9 mv offset temperature coefficient 1.7 1.7 v/c dc power supply rejection ratio 6 ?80 ?80 db v dd 10% dc crosstalk 6 28 28 v r l = 2 k. to gnd or v dd 3.5 3.5 v/ma due to load current change -7.3 -7.3 v due to powering down (per channel) output characteristics 6 output voltage range 0 v dd 0 v dd v capacitive load stability 470 470 pf r l = 1000 1000 pf r l =2 k dc output impedance 1 1 short circuit current 20 20 ma v dd =+3v coming out of power- down power-up time 10 10 ms mode. v dd =+3v reference inputs 3 reference input voltage vdd v dd v 1% for specified performance reference current 35 45 35 45 a v ref = v dd = +3.6v reference input range 0 v dd 0 v dd reference input impedance 14.6 14.6 k ?
preliminary technical data ad5666 rev. pra| page 7 of 23 reference output impedance 2 2 k ? output low voltage, v ol 0.4 0.4 v i sink = 2 ma output high voltage, v oh v dd ? 0.5 v dd ? 0.5 i source = 2 ma high impedance leakage current 1 1 a high impedance leakage current 5 5 pf power requirements v dd 2.7 3.6 2.7 3.6 v all digital inputs at 0 or v dd dac active and excluding load current i dd (normal mode) 8 0.5 3 0.5 3 ma v ih =v dd and v il =gnd i dd (all power-down modes) 9 0.2 1 0.2 1 a v ih =v dd and v il =gnd v dd =2.7 v to +3.6 v power efficiency i out /i dd 89 89 % i load =2 ma, v dd =+5 v ac characteristics 1 (v dd = +2.7 v to +3.6 v; r l = 2 k to gnd; c l = 200 pf to gnd; external vref = vdd; all specifications t min to t max unless otherwise noted) parameter 2 min typ max unit b version 1 conditions/comments output voltage settling time ad5666 8 10 s ? to ? scale settling to 2lsb settling time for 1lsb step slew rate 1 v/s digital-to-analog glitch impulse 10 nv-s 1 lsb change around major carry. see figure 21. reference feedthrough 100 db digital feedthrough 0.5 nv-s sdo feedthrough 4 nv-s daisy chain mode; sdo load is 10pf digital crosstalk 0.5 nv-s analog crosstalk 1 nv-s dac-to-dac crosstalk 3 nv-s multiplying bandwidth 200 khz vref = 2v 0.1 v p-p. total harmonic distortion -80 db vref = 2v 0.1 v p-p. frequency = 10khz output noise spectral densi ty 120 nv/hz dac code=8400 h , 1khz 100 nv/hz dac code=8400 h , 10khz output noise 15 notes 1 guaranteed by design and characterization; not production tested.
ad5666 preliminary technical data rev.pra | page 8 of 23 timing characteristics 1,2,3 (all specifications t min to t max unless otherwise noted) limit at t min , t max parameter v dd = 2.7 v to 3.6 v v dd = 3.6 v to 5.5 v unit conditions/comments t 1 1 20 20 ns min sclk cycle time t 2 11 9 ns min sclk high time t 3 9 9 ns min sclk low time t 4 13 13 ns min sync to sclk falling edge setup time t 5 4 4 ns min data setup time t 6 4 4 ns min data hold time t 7 0 0 ns min sclk falling edge to sync rising edge t 8 25 20 ns min minimum sync high time t 9 13 13 ns min sync rising edge to sclk fall ignore t 10 0 0 ns min sclk falling edge to sync fall ignore t 11 20 20 ns min ldac pulsewidth low t 12 20 20 ns min sclk falling edge to ldac rising edge t 13 20 20 ns min /clr pulse width low t 14 0 0 ns min sclk falling edge to ldac falling edge t 15 4,5 20 20 ns max sclk rising edge to sdo valid t 16 5 5 5 ns min sclk falling edge to sync rising edge t 17 5 8 8 ns min sync rising edge to sclk rising edge t 18 5 0 0 ns min sync rising edge to ldac falling edge 2 see the terminology section. 3 temperature range (y version): ?40 c to +125 c; typical at +25 c. specifications subject to change without notice. 1 3maximum sclk frequency is 50 mhz at v dd = +3.6 v to +5.5 v and 20 mhz at v dd = +2.7 v to +3.6 v. 1 guaranteed by design and characterization; not production tested. 2 all input signals are specified with tr = tf = 1 ns/v (10% to 90% of v dd ) and timed from a voltage level of (v il + v ih )/2. 3 see figures 2 and 3. 4 this is measured with the load circuit of figure 1. t 15 determines maximum sclk frequency in daisy-chain mode. 5 daisy-chain mode only. specifications subject to change without notice. i oh i ol to output pin v oh (min) c l 50pf 2ma 2ma figure 1. load circuit for digital output (sdo) t iming specifications
preliminary technical data ad5666 rev. pra| page 9 of 23 t 4 t 3 sclk sync din t 1 t 2 t 5 t 6 t 7 t 8 db31 db0 t 9 t 10 t11 t12 ldac1 ldac2 t14 notes 1. asynchronous ldac update mode. 2. synchronous ldac update mode. t13 clr figure 2. serial write operation input word for dac n db31 undefined db0 sdo t15 sclk sync din db31 t1 t4 db31 t16 t17 db0' db0 input word for dac n+1 input word for dac n 32 64 t11 t3 t2 t1 t7 t8 t9 ldac t18 figure 3. daisy chain timing diagram
ad5666 preliminary technical data rev.pra | page 10 of 23 pin configuration and fu nction descriptions sync v out a 1 2 14 13 5 6 7 10 9 8 3 4 12 11 top view (not to scale) ad5666 din gnd v dd sclk v out b v out d v out c v ref ldac clr sdo por figure 3. 14-lead tssop (ru-14) table 2. pin function descriptions pin no. mnemonic function 1 /ldac pulsing this pin low allows any or all dac registers to be updated if the input registers have new data. this allows simultaneous update of all dac outputs. alternatively, this pin can be tied permanently low. 2 /snc active low-control input. this is the frame synchroniation signal for the input data. hen snc goes low, it powers on the scl and din buffers and enables the input shift register. data is transferred in on the falling edges of the following 32 clocks. if snc is taken high before the 32nd falling edge, the rising edge of snc acts as an interrupt and the write seuence is ignored by the device. 3 dd power supply input. these parts can be operated from 2.5 to 5.5 , and the supply should be decoupled with a 10 f capacitor in parallel with a 0.1 f capacitor to gnd. 4 outa analog output oltage from dac a. the output amplifier has rail-to-rail operation. 5 outc analog output oltage from dac c. the output amplifier has rail-to-rail operation. 6 ref reference input/output pin 7 por power-onCreset pin. tying this pin to gnd powers on part to 0. tying to dd powers on part to midscale. 8 sdo serial data output. can be used for daisy-chaining a number of these devices together or for reading back the data in the shift register for diagnostic purposes. the serial data is transferred on the rising edge of scl and is valid on the falling edge of the clock. 9 /clr active low control input that loads software selectable code C zero, m idscale, fullscale - to all input and dac registers. therefore, the outputs also go to se lected code. default clears the output to 0. 10 outd analog output oltage from dac d. the output amplifier has rail-to-rail operation. 11 outb analog output oltage from dac b. the output amplifier has rail-to-rail operation. 12 gnd ground reference point for all circuitry on the part. 13 din serial data input. this device has a 32-bit shift register. data is clocked into the register on the falling edge of the serial clock input. 14 scl serial clock input. data is clocked into the input shift register on the falling edge of the serial clock input. data can be transferred at rates up to 50 mh.
preliminary technical data ad5666 rev. pra| page 11 of 23 absolute maximum ratings stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (t a = +25c unless otherwise noted) parameter rating v dd to gnd -0.3 v to +7 v digital input voltage to gnd -0.3 v to v dd + 0.3 v v out to gnd -0.3 v to v dd + 0.3 v operating temperature range industrial (b version) -40c to +105c storage temperature range -65c to +150c junction temperature (t j max) +150c tssop package power dissipation (t j max-t a )/ ja ja thermal impedance 150.4c/w lead temperature, soldering vapor phase (60 sec) +215c infrared (15 sec) +220c esd caution esd (electrostatic discharge) sensitive device. electrosta tic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge with out detection. although this product features proprietary esd protection circuitry, permanent dama ge may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. terminology relative accuracy for the dac, relative accuracy or integral nonlinearity (inl) is a measure of the maximum deviation, in lsbs, from a straight line passing through the endpoints of the dac transfer function. a typical inl vs. code plot can be seen in figure 2. differential nonlinearity differential nonlinearity (dnl) is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. this dac is guaranteed monotonic by design. a typical dnl vs. code plot can be seen in figure 3. offset error offset error is a measure of the difference between out (actual) and vout (ideal) expressed in mv in the linear region of the transfer function. offset error is measured on the ad5666 with code ??? load ed into the dac register. this is a measure of the offset error of the dac and the output amplifier (see figures 2 and 3). it can be negative or positive, and is expressed in m. zero-code error zero-code error is a measure of the output error when ero code (0000hex) is loaded to the dac register. ideally the output should be 0 . the ero-code error is always positive in the ad5660 because the output of the dac cannot go below 0 . it is due to a combination of the offset errors in the dac and output amplifier. zero-code error is expressed in m. a plot of ero-code error vs. temperature can be seen in figure 6. gain error this is a measure of the span erro r of the dac. it is the deviation in slope of the dac transfer characteristic from ideal expressed as a percent of the full-scale range. zero-code error drift this is a measure of the change in ero-code error with a change in temperature. it is expressed in /c. gain error drift this is a measure of the change in gain error with changes in temperature. it is expressed in (ppm of full-scale range)/c. full-scale error full-scale error is a measure of the output error when full-scale code (ffff hex) is loaded to the dac register. ideally the output should be dd C 1 lsb. full-scale error is expressed in percent of full-scale range. a plot of full-scale error vs. temperature can be seen in figure 6. total unadjusted error total unadjusted error (tue) is a measure of the output error
ad5666 preliminary technical data rev.pra | page 12 of 23 taking the various offset and gain errors into account. a typical tue vs. code plot can be seen in figure 4 . digital-to-analog glitch impulse digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the dac register changes state. it is normally specified as the area of the glitch in n secs and is measured when the digital input code is changed by 1 lsb at the major carry transition (7fff hex to 8000 hex). see figure 19. dc power supply rejection ratio (psrr) this indicates how the output of the dac is affected by changes in the supply voltage. psrr is the ratio of the change in out to a change in dd for full-scale output of the dac. it is measured in db. ref is held at 2 and dd is varied 10. dc crosstalk this is the dc change in the output level of one dac in response to a change in the output of another dac. it is measured with a full- scale output change on one dac while monitoring another dac. it is expressed in . reference feedthrough this is the ratio of the amplitude of the signal at the dac output to the reference input when the dac output is not being updated (i.e., ldac is high). it is expressed in db. major-code transition glitch energy major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the dac register changes state. it is normally specified as the area of the glitch in n-s and is measured when the digital code is changed by 1 lsb at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). digital feedthrough digital feedthrough is a measure of the impulse injected into the analog output of a dac from th e digital input pins of the device, but is measured when the dac is not being written to ( snc held high). it is specified in n-s and is measured with a fullscale change on the digital input pins, i.e., from all 0s to all 1s and vice versa. digital crosstalk this is the glitch impulse transferred to the output of one dac at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another dac. it is measured in standalone mode and is expressed in n-s. analog crosstalk this is the glitch impulse transferred to the output of one dac due to a change in the output of another dac. it is measured by loading one of the input register s with a full-scale code change (all 0s to all 1s and vice versa) while keeping ldac high. then pulse ldac low and monitor the output of the dac whose digital code was not changed. the area of the glitch is expressed in n-s. dac-to-dac crosstalk this is the glitch impulse transferred to the output of one dac due to a digital code change and subse uent output change of another dac. this includes both digital and analog crosstalk. it is measured by loading one of the dacs with a full-scale code change (all 0s to all 1s and vice versa) with ldac low and monitoring the output of another dac. the energy of the glitch is expressed in n-s. multiplying bandwidth the amplifiers within the dac have a finite bandwidth. the multiplying bandwidth is a measure of this. a sine wave on the reference (with full-scale code loaded to the dac) appears on the output. the multiplying bandwidth is the freuency at which the output amplitude falls to 3 db below the input. total harmonic distortion this is the difference between an ideal sine wave and its attenuated version using the dac. the sine wave is used as the reference for the dac, and the thd is a measure of the harmonics present on the dac output. it is measured in db.
preliminary technical data ad5666 rev. pra| page 13 of 23 ad5666?typical performance characteristics figure 4. typical inl plot figure 5. typical dnl plot figure 6. typical total unadjusted error plot figure 7. inl error and dnl error vs. temperature figure 8. zero-scale error and full-scale error vs. temperature figure 9. i dd histogram with v dd =3v and v dd =5v
ad5666 preliminary technical data rev.pra | page 14 of 23 figure 10. source and sink current capability with v dd =3v figure 11. source and sink current capability with v dd =5 v figure 12. supply current vs. code figure 13. supply current vs. temperature figure 14. supply current vs. supply voltage figure 15. power-down current vs. supply voltage
preliminary technical data ad5666 rev. pra| page 15 of 23 figure 16. supply current vs. logic input voltage figure 17. full-scale settling time figure 18. half-scale settling time figure 19. power-on reset to 0v figure 20. exiting power-down (800 hex loaded) figure 21. digital-to-analog glitch impulse
ad5666 preliminary technical data rev.pra | page 16 of 23 general description d/a section the ad5666 dac is fabricated on a cmos process. the architecture consists of a string dac followed by an output buffer amplifier. the parts include an internal 1.25/2.5, 10ppm/c reference with an internal gain of two. figure 22 shows a block diagram of the dac architecture. figure 22. dac architecture since the input coding to the dac is straight binary, the ideal output voltage is given by ? ? ? ? ? ? = n d ext vref v out ^ 2 ) ( ? ? ? ? ? ? ? = n d vref v out ^ 2 (int) 2 where d = decimal equivalent of the binary code that is loaded to the dac register; 0 - 65535 for ad5666 (16 bit) n = the dac resolution figure 23. resistor string resistor string the resistor string section is shown in figure 23. it is simply a string of resistors, each of value r. the code loaded to the dac register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. the voltage is tapped off by closing one of the switches connecting the string to the amplifier. because it is a string of resistors, it is guaranteed monotonic. output amplifier the output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0 to dd . it is capable of driving a load of 2 k in parallel with 1000 pf to gnd. the source and sink capabilities of the output amplifier can be seen in figure 10 and figure 11. the slew rate is 1 /s with a half-scale settling time of 8 s with the output unloaded. serial interface the ad5666 has a three-wire serial interface ( snc , scl and din), which is compatible with spi, spi and microire interface standards as well as most dsps. see figure 2 for a timing diagram of a typical write seuence. the write seuence begins by bringing the snc line low. data from the din line is clocked into the 32-bit shift register on the falling edge of scl. the serial clock freuency can be as high as 50 mh, making the ad5666 compatible with high speed dsps. on the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed (i.e., a change in dac register contents and/or a change in the mode of operation). at this stage, the snc line may be kept low or be brought high. in either case, it must be brought high for a minimum of 33 ns before the next write seuence so that a falling edge of snc can initiate the next write seuence. since the snc buffer draws more current when in 2 than it does when in 0.8 , snc should be idled low between write seuences for even lower power operation of the part. as is mentioned above, however, it must be brought high again just before the next write seuence. input shift register the input shift register is 32 bits wide (see figure 24). the first five bits are dont cares. the next three bits are the command bits c2-c0, (see table 1) followed by the 4-bit dac address a3-a0, (see table 2) and finally the 16-bit data word. the data word comprises the 16- bit input code followed by 4 dont care bits for the ad5666. see figure 24. these data bits are transferred to the dac register on the 32nd falling edge of
preliminary technical data ad5666 rev. pra| page 17 of 23 sclk. daisy-chaining for systems that contain several dacs, or where the user wishes to read back the dac contents for diagnostic purposes, the sdo pin may be used to daisy-chain several devices together and provide serial readback. the the daisy chain mode is enabled through a software executable dcen setup function, command 1000 is reserved for this dcen setup function, see table 3. the daisy chain mode is software-programmable by setting a bit (db1) in the dcen setup register. the default setting is stand-alone mode where bit dcen =0. table 4 shows how the state of the bits corresponds to the mode of operation of the device. input shift register when sync is low. if more than 32 clock pulses are applied, the data ripples out of the shift register and appears on the sdo line. this data is clocked out on the rising edge of sclk and is valid on the falling edge. by connecting this line to the din input on the next dac in the chain, a multi-dac interface is constructed. thirty-two clock pulses are required for each dac in the system. therefore, the total number of clock cycles must equal 32n, where n is the total number of devices in the chain. when the serial transfer to all devices is complete, sync should be taken high. this prevents any further data from being clocked into the input shift register. a continuous sclk source may be used if it can be arranged that sync is held low for the correct number of clock cycles. alternatively, a burst clock containing the exact number of clock cycles may be used and sync may be taken high some time later. when the transfer to all input registers is complete, a common ldac signal updates all dac registers and all analog outputs are updated simultaneously. address bits command bits c3 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x x x x xxx x db0 (lsb) figure 24a ad5666. input register contents command c3 c2 c1 c0 0 0 0 0 rite to input register n 0 0 0 1 update dac register n 0 0 1 0 rite to input register n, update all 0 0 1 1 rite to and update dac channel n 0 1 0 0 power down dac (power-up) 0 1 0 1 load clear code register 0 1 1 0 load ldac register
ad5666 preliminary technical data rev.pra | page 18 of 23 (ldac overwrite) 0 1 1 1 reset (power-on-reset) 1 0 0 0 dcen/ref setup register 1 0 0 1 reserved * * * * reserved 1 1 1 1 reserved table 1. command definition address (n) a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 1 1 1 1 all dacs table2. address command snc interrupt in a normal write seuence, the snc line is kept low for at least 32 falling edges of scl and the dac is updated on the 32nd falling edge. however, if snc is brought high before the 32nd falling edge this acts as an interrupt to the write seuence. the shift register is reset and the write seuence is seen as invalid. neither an update of the dac register contents or a change in the operating mo de occurssee figure 25. db31 db0 scl snc din db31 db0 alid rite seuence, output updates inalid rite seuence snc high before 32 nd falling edge on the 32 nd falling edge figure 25. snc interrupt facility reference setup Cexternal to internal the on-board reference is turned off at po wer-up by default, allowing the use of an external reference. the ad5666 has an on-c hip reference with an internal ga in of two. the ad5666-1 has a 1.25 10ppm/c max reference and the ad5666-2 has a 2.5 10ppm/c max reference. the on-board reference can be turned on/off through a software ex ecutable ref setup function, command 1000 is reserved for this ref setup function, see table 3. the reference mode is software-programmable by setting a bit (db0) in the ref
preliminary technical data ad5666 rev. pra| page 19 of 23 setup register. table 4 shows how the state of the bits corresponds to the mode of operation of the device. dcen/ref setup register dcen (db1) ref (db0) action 0 0 stand-alone mode C ref off 0 1 stand-alone mode C ref on 1 0 dcen mode C ref off 1 1 dcen mode C ref on table 3. daisy chain enable /reference set-up register msb lsb db31 C db28 db27 db26 db25 db24 db23 db22 db21 db20 db2- db19 db1 db0 x 1 0 0 0 x x x x x 1/0 1/0 dont cares command bits (c3-c0) address bits (a3 C a0) dont cares dcen/ref setup register table 4. 32-bit input shift register contents for daisy chain enable and reference setup function power-on-reset the ad5666 family contains a power-on-reset circuit that controls the output voltage during power-up. by connecting the por pin low the dac output powers up to ero volts an d by connecting the por pin high the dac output powers up to midscale. the output remains there until a valid write seuence is made to the dac. this is useful in applications where it is important to know the state of the output of the dac while it is in the process of powering up. there is also a software executable reset function that will reset the dac to the power-on -reset code. command 111 is reserve d for this reset function, see table 1. power-down modes the ad5666 contains four separate modes of operation. command 100 is reserved for the power-down function. see table 1. these modes are software-programmable by setting two bits (db19 and db18) in the control register. table 3 shows how the state of the bits corresponds to the mode of operation of the device. any or all dacs, (dacd to daca) may be powered down to the selected mode b y setting the corresponding 4 bits (db7,6,1,0) to a 1. see table 6 for contents of the input shift register during power down /up operation. hen both bits are set to 0, the part works normally with its no rmal power consumption of 250 a at 5 . however, for the three power- down modes, the supply current falls to 200 na at 5 (50 na at 3 ). not only does the supply current fall but the output stag e is also internally switched from the output of the amplifier to a resist or network of known values. this has the advantage that the out put
ad5666 preliminary technical data rev.pra | page 20 of 23 impedance of the part is known while the part is in power-down mode. there are three different options. the output is connected internally to gnd through a 1 k ? ? resistor, a 100 k ? ? db9 db8 operating mode 0 0 normal operation power down modes 0 1 1 k to gnd 1 0 100 k to gnd 1 1 three state table 3. modes of operation for the ad5666 msb lsb db31 C db28 db27 db26 db25 db24 db 23 db22 db21 db20 db10 db19 db9 db8 db4- db7 db3 db2 db1 db0 x 0 1 0 0 x x x x x pd1 pd0 dacd dacc dacb daca dont cares command bits (c2-c0) address bits (a3 C a0) dont cares dont cares power down mode dont cares power down/up channel selection C set bit to a 1 to select table 6. 32-bit input shift register contents of power up/down function clear code register the ad5666 gives the option of clearing any on e or all dac channels to 0, midscale or fullscale code. command 101 is reserved f or the clear code function. see table1. these clear code values are software-programmable by setting two bits (db1 and db0) in the control register. table shows how the state of the bits corresponds to the clear code values of the device. upon execution of the h ardware /clr pin (active lo), the dac output is cleared to the clear code re gister value (default setting is ero). see table 7 for cont ents of the
preliminary technical data ad5666 rev. pra| page 21 of 23 input shift register during the clear code register operation clear code register cr1 cr0 clears to code 0 0 0000h 0 1 8000h 1 0 ffffh 1 1 no operation table 6. clear code register msb lsb db31 C db28 db27 db26 db25 db24 db 23 db22 db21 db20 db2- db19 db1 db0 x 0 1 0 1 1/0 1/0 1/0 1/0 x 1/0 1/0 dont cares command bits (c2-c0) address bits (a3 C a0) dont cares clear code register (cr1- cr0) table 7. 32-bit input shift register contents clear code function ldac function the outputs of all dacs may be updated simult aneously using the hardware /ldac pin. synchronous ldac: h dac rsrs r u r n s r n on h n o h n scl us ldac cn rnny o or us s n ur asynchronous ldac: h ouus r no u h s h h nu rsrs r rn o hn ldac os o h dac rsrs r u h h conns o h nu rsr h ouus o dacs y u sunousy usn h ldac uncon h h uncony o scn hro uh sor ny nur o dac ch nns o synchron rn o h dac usn con h hrr ldac n cn orrn y sn h s o h ldac rsr dd dd s or h ldac o o oron h u or ch chnn s ldac n ors nor y sn h s o ns h dac chnn u rrss o h s o h ldac n hs s h n o on ny conon o chnns o synchronousy u s or conns o h nu sh sr urn h ldac orr o o oron lo dac ldacs d d ldac ldac ron drn y ldac n don cr dac chnns u orrn h ldac n table 5. ldac overwrite definition
ad5666 preliminary technical data rev.pra | page 22 of 23 msb lsb db31 ? db28 db27 db2 6 db2 5 db2 4 db2 3 db2 2 db2 1 db2 0 db4 ?db19 db3 db2 db1 db0 x 0 1 1 0 x x x x x dacd dacc dacb daca don?t cares command bits (c2-c0) address bits (a3 ? a0) don?t cares don?t cares setting /ldac bit to ?1? overwrites /ldac pin table 8. 32-bit input shift register co ntents for /ldac overwrite function power supply bypassing and grounding hen accuracy is important in a circuit it is helpful to carefully consider the power supply and ground return layout on the board. the printed circuit board containing the ad5666 should have separate analog and digital sections, each having its own area of the board. if the ad5666 is in a system where other devices reuire an agnd to dgnd connection, the connection should be made at one point only. this ground point should be as close as possible to the ad5666. the power supply to the ad5666 should be bypassed with 10 f and 0.1 f capacitors. the capacitors should be physically as close as possible to the device with the 0.1 f capacitor ideally right up against the device. the 10 f capacitors are the tantalum bead type. it is important that the 0.1 f capacitor has low effective series resistance (esr) and effective series inductance (esi), e.g., common ceramic types of capacitors. this 0.1 f capacitor provides a low impedance path to ground for high freuencies caused by transient currents due to internal logic switching. the power supply line itself should have as large a trace as possible to provide a low impedance path and reduce glitch effects on the supply line. clocks and other fast switching digital signals should be shielded from other parts of the board by digital ground. avoid crossover of digital and analog signals if possible. hen traces cross on opposite sides of the board, ensure that they run at right angles to each other to reduce feedthrough effects through the board. the best board layout techniue is the microstrip techniue where the component side of the board is dedicated to the ground plane only and the signal traces are placed on the solder side. however, this is not always possible with a two-layer board.
preliminary technical data ad5666 rev. pra| page 23 of 23 outline dimensions 14 8 7 1 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 0 figure 26. 14-thin shrink sm all outline package [tssop] (ru-14) dimensions shown in millimeters ordering guide model bit internal reference package option1 ad5666bruz-1 16 1.25 ru-14 ad5666bruz-2 16 2.5 ru-14 ad5666aruz-2 16 2.5 ru-14 1 thin shrink small outline package (tssop) ? 2003 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective companies. printed in the u.s.a. pr05298-0-12/04(pra)

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